FIG. 20 shows a prior art semiconductor device. In FIG. 20, reference numeral 1 designates a semiconductor chip, reference numeral 2 designates a substrate material such as a lead frame, and reference numeral 3 designates solder for junctioning the semiconductor chip 1 to the substrate material 2. In such a semiconductor device, a semiconductor chip 1 and a substrate material 2 are held putting the solder 3 therebetween, and the solder 3 is heated to be melted to a temperature higher than its melting point and thereafter it is cooled to junction the semiconductor chip 1 to the substrate material 2. This is a so called solder die-bonding method. Such kind of solder die-bonding method is disclosed in "Microassembly technique for a semiconductor device; Trikeps technical material No. 76 (July 1982)."
In the above-described prior art junctioning method for a semiconductor device, since the solder 3 is in a melted state at the junctioning, the interval between the semiconductor chip 1 and the substrate 2 after the junctioning becomes about 10 to 20 microns and even if a large quantity of solder 3 is supplied between the semiconductor chip 1 and the substrate material 2 so as to widen the interval therebetween, almost all the solder would be exhausted at the melting and it was difficult to control the interval at a desired value from the outside. In addition, the interval between the semiconductor chip 1 and the substrate material 2 is ought to be reduced due to the wetting and broadening of the solder 3 and if solder is supplementarily supplied, there arises a positional deviation of the semiconductor chip 1 accompanying the flow of the solder 3, resulting in a problem in the later wire bonding process.
As described above, it was impossible to stably control the interval between the semiconductor chip 1 and the substrate material 2 at a desired value. Further, when the anti-heat property is required for the junction part in the later process, the solder 3 having a melting point higher than the temperature for which the anti-heat property is required is used for the junctioning and, then the higher the melting point is, the higher the junction temperature is, thereby resulting in a large thermal stress occurring due to the difference in the thermal expansion coefficients between the semiconductor chip 1 and the substrate material 2. Especially, when a silicon semiconductor chip is used for the semiconductor chip 1 and a copper system lead frame is used for the substrate material 2, the thermal expansion coefficient of the copper system lead frame amounts to a value five times as that of the silicon semiconductor chip 1, causing a destruction of the semiconductor chip 1 due to the residual stress remaining direct after the junctioning and the thermal stress in the environment when used thereafter. This phenomenon is eminent for a semiconductor chip 1 having a size larger than three millimeters square. In addition, when compound semiconductor is used for the semiconductor chip 1, there may be a case where the semiconductor chip is damaged even when the thermal expansion coefficient difference between the semiconductor chip 1 and the substrate material 2 is low because the compound semiconductor is mechanically weak with relative to the silicon semiconductor, thereby leading to a large difficulty in the soldering.